Embodiments of the present invention relate to integrated circuits in general and, in particular, to a calibrated transfer rate for circuit configuration data. One of the success factors in the design and development of integrated circuits is the ability to adapt to new functional requirements in next generation electronic products. Traditional ways to reduce the time taken to introduce new products is to increase the available development resources and subdivide tasks to perform them in parallel. Additionally, circuits can be designed so that they can be reconfigured quickly. Successful reconfigurable architectures include masked ROM, gate-arrays, and analog arrays where logic, memory content, or analog building block interconnects and attributes can be changed by modifying a subset of the normal process layers, typically in the metal interconnect layers.
The introduction of nonvolatile programming technology such as electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and one-time-programmable (OTP) antifuse have allowed this type of reconfiguration to be done through electrical programming rather than through wafer fabrication that may require reticle changes for implementation. When using electrical programming technology to change circuitry, it may be beneficial to have configuration information available in near “real time” fashion and at many different control or reconfiguration points within a circuit. Memory support circuits, such as data busses, address decoders, sense amplifiers, and high voltage control circuits, may be used in proximity to the respective die locations in order to support every bit used in circuit configuration. Therefore, the nonvolatile memory “bit” information is sometimes stored in multiple locations throughout the semiconductor die, which may lead to an inefficient nonvolatile memory structure.
In light of the foregoing, it may be desirable to have an architecture where some configuration data is stored in a more centralized memory and distributed upon power-up. Moreover, it may be desirable to identify novel techniques in which the configuration data is distributed more quickly and/or efficiently during system power-up.